MB85RC64
■ DATA STRUCTURE
In the I 2 C bus, the acknowledge “L” is output on the 9th bit after the 8 bits of the device and address word
following the start condition. After confirming the acknowledge response at the slave, the I 2 C master outputs
8bits × 2 memory address to the I 2 C slave. When the memory address input ends, the slave again outputs
the acknowledge “L”. After this operation, the I/O data follows in units of 8 bits, with the acknowledge “L”
output after every 8bits.
It is determined by the R/W code whether the data line is driven by the master or the slave. For a write
operation the slave will accept 8bits from the master then send an acknowledge. If the master detects the
acknowledge, the master will transfer the next 8bits. For a read operation the slave will place 8bits on the
I 2 C bus, then wait for an acknowledge from the master.
? Data Structure Diagram
Start
1
2
3
4
5
6
7
8
9
1
2
SCL
SDA
ACK
..
S
1
0
1
0
A2
A1
A0
R/ W
A
..
Access from master
Access from slave
S Start Condition
A ACK
■ FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED
The MB85RC64 performs write operations at the same speed as read operations, so any waiting time for
an ACK polling* does not occur. The write cycle takes no additional time.
*: As to E 2 PROM, the Acknowledge Polling is performed as a progress check in the write programming step.
It places NAK condition on the bus as of “not acknowledged” during the writing programming period. The
busy status for the write programming is given from 9th ACK bit. That “done” condition is placed onto I 2 C
bus by E 2 PROM I 2 C device and your program had to poll the bus in order to sense that condition.
■ WRITE PROTECT (WP)
The entire memory array can be write protected using the Write Protect pin. When the Write Protect pin is
set to “H”, the entire memory map will be write protected. When the Write Protect pin is “L”, all addresses
may be overwritten. Reading is allowed regardless of the WP pin's High/Low.
Note : The Write Protect pin is pulled down internally to VSS pin, therefore if the Write Protect pin is open, the
pin status is detected as Low (write enabled).
DS05–13109–3E
7
相关PDF资料
MB85RS128APNF-G-JNE1 IC FRAM 128KBIT 25MHZ 8SOP
MB85RS64PNF-G-JNE1 IC FRAM 64KBIT 20MHZ 8SOP
MC10SX1130DR2 IC LED DRIVER LINEAR 16-SOIC
MC33152DG IC DRIVER MOSFET DUAL HS 8SOIC
MC33153PG IC DRIVER GATE SINGLE IGBT 8DIP
MC34151DG IC MOSFET DRIVER DUAL HS 8SOIC
MC34844EP IC LED DVR BACKLIGHT 10CH 32QFN
MC34845AEPR2 IC LED DVR BACKLIGHT 6CH 24QFN
相关代理商/技术参数
MB85RC64PNF-G-JNERE1 制造商:FUJITSU 功能描述:64K(8K8) bit,I2C,Memory FRAM
MB85RC64TAPNF-G-BDERE1 功能描述:IC FRAM 64KBIT 3.4MHZ 8SOP 制造商:fujitsu electronics america, inc. 系列:- 包装:剪切带(CT) 零件状态:在售 存储器类型:非易失 存储器格式:FRAM 技术:FRAM(铁电体 RAM) 存储容量:64Kb (8K x 8) 时钟频率:3.4MHz 写周期时间 - 字,页:- 存储器接口:I2C 电压 - 电源:1.8 V ~ 3.6 V 工作温度:-40°C ~ 85°C(TA) 安装类型:表面贴装 封装/外壳:8-SOIC(0.154",3.90mm 宽) 供应商器件封装:8-SOP 标准包装:1
MB85RC64TAPN-G-AWERE1 功能描述:IC FRAM 64KBIT 3.4MHZ 8SON 制造商:fujitsu electronics america, inc. 系列:- 包装:剪切带(CT) 零件状态:在售 存储器类型:非易失 存储器格式:FRAM 技术:FRAM(铁电体 RAM) 存储容量:64Kb (8K x 8) 时钟频率:3.4MHz 写周期时间 - 字,页:- 存储器接口:I2C 电压 - 电源:1.8 V ~ 3.6 V 工作温度:-40°C ~ 85°C(TA) 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商器件封装:8-SON 标准包装:1
MB85RC64V 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:64 K (8 K??8) ?????????I2C
MB85RC64VPNF-ES-JNE1 制造商:FUJITSU 功能描述:
MB85RC64VPNF-G-JNE1 制造商:FUJITSU 功能描述:
MB85RC64VPNF-G-JNERE1 制造商:FUJITSU 功能描述:IC FRAM 64KBIT I2C 8SOP 制造商:FUJITSU 功能描述:64K(8K8) bit,I2C,Memory FRAM
MB85RQ4MLPF-G-BCERE1 功能描述:IC FRAM 4MBIT 108MHZ 16SOP 制造商:fujitsu electronics america, inc. 系列:- 包装:剪切带(CT) 零件状态:在售 存储器类型:非易失 存储器格式:FRAM 技术:FRAM(铁电体 RAM) 存储容量:4Mb (512K x 8) 时钟频率:108MHz 写周期时间 - 字,页:- 存储器接口:SPI - 四 I/O 电压 - 电源:1.7 V ~ 1.95 V 工作温度:-40°C ~ 85°C(TA) 安装类型:表面贴装 封装/外壳:16-SOIC(0.295",7.50mm 宽) 供应商器件封装:16-SOP 标准包装:1